This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to an electrically programmable read only memory (EPROM) of the floating gate type.
Nonvolatile memory devices using a floating gate to retain charge are made by a double level polysilicon process as set forth in U.S. Pat. No. 4,122,544 issued to David J. McElroy and U.S. Pat. No. 4,112,509 issued to Lawrence S. Wall, both assigned to Texas Instruments, or in U.S. Pat. No. 3,984,822 issued to Simko et al. Other EPROM and electrically erasable EPROM cells and processes are shown in pending applications Ser. No. 957,518, filed Nov. 2, 1978, by Kuo and Tsaur and Ser. No. 1,097, filed Jan. 5, 1979, by Guterman and Chiu, both assigned to Texas Instruments. Some of these types of devices are widely used in microcomputers, particularly in program development.
The stacked gate structure of these prior EPROM cells include a first level polysilicon floating gate memory element and a second level poly control gate, producing a transistor which is inherently of lower gain than a comparable standard single-level silicon gate device, due to three factors. First, the channel is doped P+ to enhance programming efficiency, at the expense of reduced K' in linear operation. Second, high channel doping results in earlier saturation as indicated by the larger alpha, usually about 2.0, whereas for lightly doped channels alpha is approximately unity; the drain voltage at saturation is approximately equal to gate voltage minus threshold voltage divided by alpha. Third, the channel is controlled directly by the floating gate, whose potential is governed in turn by the applied control gate voltage and the capacitance coupling ratio from floating to control gate vs. total capacitance seen by the floating gate, given to first approximation by: ##EQU1##
Where Cf-c is the capacitance between the floating gate and the control gate and Cf-ch is the capacitance between the floating gate and the channel. The floating gate in effect shields the channel from the control gate, since it is a conductor, so the only way the voltage on the control gate can influence the channel is by capacitive coupling to the floating gate. If the capacitances are equal in the above formula, the coupling ratio is 50%, so one-half the control gate voltage is coupled to the floating gate and a 5 V logic level becomes a 2.5 V level as seen by the channel. Typical coupling factors in EPROM devices now in volume production having 0.2 mil channel widths and 0.15 mil overlap on each side onto field oxide can exceed 65%. The coupling ratio is of course a function of the dielectric thickness in the two capacitors as formed by gate oxide and interlevel oxide. For those production devices, the ratio of dielectric thickness is about 1.3 interlevel to 1.0 gate because the oxide thicknesses are about 1000 and 800 A, respectively. To increase the coupling ratio, significant portions of the floating gate must extend out over field oxide and be overlapped by the second level poly control gate, requiring excess spacing for alignment. Further, as the cell size is reduced for higher cell density, as for a 128K bit device, the channel widths become much narrower, helping the coupling ratio but causing low and poorly controlled channel width-to-length ratios.
It is, therefore the principal object of this invention to provide an improved electrically programmable memory, particularly with improved coupling ratio. Another object is to provide an EPROM of reduced cell size. An additional object is to provide a dense array of EPROM cells having improved characteristics, made by a more efficient method.